module if_stage(
    input clk,
    input reset,
    //allwoin
    input ds_allowin     ,
    //brbus
    input [32:0] br_bus         ,
    //to ds
    output        fs_to_ds_valid ,
    output [63:0] fs_to_ds_bus   ,
    // inst sram interface
    output        inst_sram_en   ,
    output [ 3:0] inst_sram_we  ,
    output [31:0] inst_sram_addr ,
    output [31:0] inst_sram_wdata,
    input  [31:0] inst_sram_rdata
    );

reg         fs_valid;
wire        fs_ready_go;
wire        fs_allowin;

wire [31:0] seq_pc;
wire [31:0] nextpc;

wire         br_taken;
wire [ 31:0] br_target;
assign {br_taken,br_target} = br_bus;

wire [31:0] inst;
reg  [31:0] pc;
assign fs_to_ds_bus = {inst ,
                       pc   };

assign fs_ready_go = 1'b1;
assign fs_allowin = (~fs_valid) | (fs_ready_go & ds_allowin);
assign fs_to_ds_valid = fs_valid & fs_ready_go;
    //pre-IF
assign seq_pc       = pc + 3'h4;
assign nextpc       = br_taken ? br_target : seq_pc;

always @(posedge clk) begin
    if (reset) begin
        pc <= 32'h1bfffffc; 
    end
    else if(fs_allowin) begin
        pc <= nextpc;
    end
end

always @(posedge clk ) begin
    if (reset) begin
        fs_valid <= 1'b0;
    end
    else if (fs_allowin) begin
        fs_valid <= 1'b1;
    end
    else if(br_taken)begin
        fs_valid <= 1'b0;
    end
end
assign inst_sram_en    = fs_allowin;
assign inst_sram_we    = 4'b0000;
assign inst_sram_addr  = nextpc;
assign inst_sram_wdata = 32'b0;
assign inst            = inst_sram_rdata;

endmodule
